Power Architecture and Optimization Engineer – New College Grad 2025
NVIDIA
On-site 🏢 24 September
R&D, Innovation
California, United States 🇺🇸 Texas, United States 🇺🇸
We are now looking for a Power Architecture and Optimization Engineer – New College Grad! NVIDIA prides in having energy efficient products. We believe in continuing to maintain our products' energy efficiency compared to competition is key to our continued success.
Our team is privileged to work on Power Optimization of Data center, gaming and automotive GPU chips. We also work on power optimization of Networking chips. The gamut of GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Networking products. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
What You'll Be Doing:
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
Develop and share best practices for performing pre-silicon power analysis.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype a new architectural feature in Verilog and analyze power.
What We Need To See:
Pursuing BS or MS in Electrical Engineering, Computer Engineering, or related fields.
Strong understanding of concepts of energy consumption, estimation, data movement and low power design.
Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect). Previous internships and/or work on Power Optimization would be beneficial.
Strong coding/automation skills, preferably in Python, Perl, and C++.
Strong analytical skills with go-getter attitude.
You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.
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